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Enhancement/Depletion Decoder Circuit

IP.com Disclosure Number: IPCOM000086669D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 53K

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Related People

Dockerty, RC: AUTHOR [+2]


This is an improved decoder and driver circuit for field-effect transistor (FET) memories.

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Enhancement/Depletion Decoder Circuit

This is an improved decoder and driver circuit for field-effect transistor (FET) memories.

In FET memory circuits, the delay through decoders (word and bit decoders) frequently limits the overall access time of the memory. By using enhancement/depletion (E/D) FET technology, delay through decoders, as well as other memory peripheral circuits, is reduced. A desirable design, however, must improve the speed without increasing power consumption. In order to reduce high DC power consumption, dynamic circuits are preferred and the use of depletion-mode devices to charge up the various circuit nodes provides the full supply voltage to these nodes. Furthermore, depletion-mode devices used in a switched configuration permit a rapid charging of these circuit nodes. An advantageous use of depletion-mode devices further requires that they be periodically turned off, which is achieved by providing a sufficient gate-to-source bias.

In Fig. 1, transistors T1, T2, T3, T4 and T5 are enhancement-mode devices connected in a NOR-logic configuration. Transistors T6 and T7 are depletion-mode devices, while transistor T8 is an enhancement-mode device with a gate-to-source bootstrap capacitor CB and a capacitive load illustrated by the capacitance CL.

The depletion-mode devices T6 and T7 permit nodes 1 and 2 to be raised to a full logic up level (VH), improving the overall operation as illustrated in Fig. 2. Transistor T6 receives a pulse input CX,...