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# Synchronized Clocking System

IP.com Disclosure Number: IPCOM000086789D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 108K

IBM

## Related People

Gindi, AM: AUTHOR [+1]

## Abstract

This system relates to the failure detection of 1 of n independent synchronized clocks. The use of plural clocks is an availability measure. The clocks are feedback cross-coupled one to the other in order to provide synchrony in phase and frequency such that the detected failure of one permits the switchable replacement of another. Also, in a two-clock system, if A is perceived as failing when, in fact, B is failing, there exists a finite probability of total failure, since B would be switched to replace A.

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Synchronized Clocking System

This system relates to the failure detection of 1 of n independent synchronized clocks. The use of plural clocks is an availability measure. The clocks are feedback cross-coupled one to the other in order to provide synchrony in phase and frequency such that the detected failure of one permits the switchable replacement of another. Also, in a two-clock system, if A is perceived as failing when, in fact, B is failing, there exists a finite probability of total failure, since B would be switched to replace A.

The solution contemplates using an odd number of distinguishable clocks in successive comparison pairs, e.g., three, and a logic arrangement. The method herein described will detect a loss of synchrony by one of the clocks due to a change in frequency, or due to an abrupt and complete failure of one of the clocks. The method for detecting which one of 3 clocks A, B or C is out of sync comprises the steps of: (1) generating at least four sequential clock pulses from each clock; (2) setting/resetting alternately a common flip-flop (FF) with the first pulse from clock A setting the FF and the third pulse from clock B resetting the FF; (3) sampling the FF output Q with the second pulse from clock B and sampling FF output 0 with the fourth pulse from clock A, such that if the FF is in a reset state at T2 time or in a set state at T4 time, then an out-of-sync condition is registered, otherwise clocks A and B are in sync; (4) repeating steps (1), (2) and
(3) for each pair; and (5) detecting the defective clock by elimination. Note, step
(5) devolves from identifying the common element in successive failure comparisons, i.e., AB, BC, then B is defective.

It is an interesting consequence that for n clocks, one need only make n comparisons, instead of n* = n!/(n-2)!2!(*

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Referring now to Fig. 1, there is shown a pair of cross-coupled clocks 7 and 19 implemented as crystal-controlled oscillators A and B. Each oscillator is driven by phase detection and correction circuitry, 1 and 13, respectively. The oscillators are voltage controlled such that a signal on paths 3 and 5 to A and 15 and 17 to B constitutes a correction signal to fractionally cycle increase/decrease the resonant frequency as a function of the phase difference detected on the input, i.e., to phi detector 1, lines 9b and 11b, to phi detector 13, lines 9a and 11a. A and B are cross-coupled over respective paths 9a and 11b and self- coupled over 9b and 11a. Detectors 1 and 13 also house the logic ar...