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# General Computer Logic Graph Analyzer

IP.com Disclosure Number: IPCOM000087164D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 14K

IBM

## Related People

Feuer, M: AUTHOR [+2]

## Abstract

In many design problems it is necessary to test the effectiveness of design algorithms and programs and of proposed package images earlier than when the actual functional computer logic is available. Thus, there is a need for analysis and synthesis (or generation) of "artificial" or nonfunctional computer logic graphs of arbitrarily large size, which can be used to test the programs and images under consideration.

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General Computer Logic Graph Analyzer

In many design problems it is necessary to test the effectiveness of design algorithms and programs and of proposed package images earlier than when the actual functional computer logic is available. Thus, there is a need for analysis and synthesis (or generation) of "artificial" or nonfunctional computer logic graphs of arbitrarily large size, which can be used to test the programs and images under consideration. In order to analyze real and artificial computer logic and synthesize artificial computer logic, two basis questions must be investigated:
(1) What parameters are to be used to characterize the

computer

logic, and thus are the quantities to be analyzed or

determined?
(2) How are these parameters related to each other such

such that

artificial graph can be generated to properly simulate

the topological

and some functional characteristics of a real

functional computer logic graph? This article describes a logic graph analyzer which can be used to investigate these two questions.

Given the net list of logic blocks in which the nets and blocks are labeled sequentially from one to their maximum number, the analyzer determines values for the following topological and functional variables of combinational or sequential computer logic graphs: (1) number of logic blocks; (2) number of nets;
(3) number of primary input nets; (4) number of primary output nets; (5) number of output pins per each logic block and average value thereof; (6) number of dots per each net and average value thereof; (7) number of logic blocks per each net and average value thereof; (8) number of nets per each logic block and average values thereof; (9) number of independent feedback loops (i.e., minimal set of loops or "cutset"); (10) number and identity of logic blocks per each loop and average value thereof; (11) number of logic levels; and (12) number and identity of logic blocks and number of primary output nets and feedback loops per each logic level.

For sequential logic, the analyzer employs an efficient and accurate heuristic (may be an...