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Elimination of False Error Signals Disclosure Number: IPCOM000087349D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 45K

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Aichelmann, FJ: AUTHOR [+2]


This is an error detection technique for determining the half-word location of a parity error.

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Elimination of False Error Signals

This is an error detection technique for determining the half-word location of a parity error.

Error-correction codes (ECC) are incorporated into most monolithic memories to insure operation reliability. Memories requiring these error-correction codes are either full word or double word widths, in order to minimize the required number of check bits. The data bus that is used to communicate between the basic storage module (BSM) and the engine may not have the same data width. Fig. 1 illustrates a typical engine-BSM-monolithic storage array interconnection and data flow.

As a result of the bandwidth bus difference between the engine and BSM, it is possible for errors (both correctable and not correctable) to occur within the memory data transfer boundary between the monolithic storage arrays and BSM (full word), but not reside in the requested address boundary between the SM and engine (half word). This results in signalling a noncorrectable multiple error detection (MED) error, regardless of its half word location, and causing the engine to take a subsequent program interruption (machine check). This reported MED error may not be valid because it could reside in a half word that was not requested by the engine.

By assigning check bits to exclusive parity coverage across the first or second half words, certain multiple errors can be identified within specific half words so that the engine can distinguish between valid and invalid memory address errors, thereby avoiding unnecessary interruptions.

For instance, in a four byte memory data bus, when assigning check bits (Cj) for t...