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# Circuit Network Test

IP.com Disclosure Number: IPCOM000088451D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 41K

IBM

## Related People

Muehldorf, EI: AUTHOR [+1]

## Abstract

Described is a method of determining whether a set of test patterns will propagate through a network and can be applied to the terminals of a second network.

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Circuit Network Test

Described is a method of determining whether a set of test patterns will propagate through a network and can be applied to the terminals of a second network.

In modern LSI (large-scale integration) macro designs it is desirable to apply test patterns directly at the macro boundaries
(i.e., macro inputs) and compute the responses for the macro outputs. Similarly, for logic with embedded arrays, the array pattern must be applied through logic and the test results at the array outputs must be propagated through logic to primary outputs. It is assumed that the logic design is following the LSSD (Level Sensitive Scan Design) Rules [1]. In either case, i.e., macro design and embedded array designs are in accord with the rules given in [1].

Fig. 1 shows the structure of logic with embedded arrays. The following requirement is placed on the combinatorial logic network blocks A and B: There must be a one-to-one mapping of the input patterns onto the output patterns. That is to say, if a logic network L (Fig. 2) has m inputs, there are 2/m/ different patterns that can be applied to the network inputs. The response at the network must now consist of exactly 2/m/ different patterns, each output pattern corresponding to exactly one input pattern.

It is an important question as to how a combinatorial logic circuit network can be analyzed in order to determine whether the one-to-one mapping property exists for a given network.

For this purpose the n outputs of a combinatorial logic network L are expressed as n functions of the input variables: Y(1) = Y(1) (X(1) .... X(m))

Y(2) = Y(2) (X(1) .... X(m))

Y(n) = Y(n) (X(1) .... X(n)). As the next step, one generates the derivatives [2] of each output function with respect to each of the input variables. The derivatives which are used for the purpose discussed here are the Boolean difference, such as given in [3, 4,
5]. The Boolean difference of first order,

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Delta Y(i) over Delta X(i) is termed S(ij)/(1)/. Then one arranges all Boolean differences to a first order switching matrix S/(1)/ as follows:. #

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As the next step, one forms the Boolean row sums in the switching matrix. These are

1

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where Sigma indicates the Boolean sums, i.e, the logic "OR" function. There are exactly m such row sums of first order where each row sum of first order expresses the conditions under which a single input change at input i is transmitted to any one or more of the n outputs.

Finally, one forms the first order intersection of row sums. #

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where Pi indicates...