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Embedded Macro Test Pattern Generation Disclosure Number: IPCOM000088452D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 71K

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Muehldorf, EI: AUTHOR [+2]


Described is a method of generating tests for a set of multiple macros embedded in logic or an LSI chip.

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Embedded Macro Test Pattern Generation

Described is a method of generating tests for a set of multiple macros embedded in logic or an LSI chip.

The design approach to LSI chips may be described as follows: The machine logic is subdivided into functional macros such as PLAs, registers, bus structures and the like. For each of these macros a physical embodiment is generated. The physical macros are then arranged closely to each other to generate a chip image.

Fig. 1 illustrates the logic breakdown and the physical synthesis. The logic chip comprises an ALU, a counter and a control section, each of which is decomposed into macros. Each of the macros is then physically implemented and shown as part of the chip image.

When it comes to test pattern generation it would be desirable to generate test patterns for each macro and then combine the test patterns to obtain test patterns on a chip level. It has been found that this is possible only in exceptional cases where some specific design constraints are imposed.

A typical structure of the macro chip as seen from the viewpoint of test pattern generation is shown in Fig. 2. This figure shows one basic assumption - the logic follows the LSSD (Level Sensitive Scan Design) guidelines [1]. One can recognize that all registers are connected to a scan path. That reduces the problem to finding only a method for generating tests for the combinatorial logic macros, i.e., the PLAs, busses and other purely combinatorial structures.

In order to use an approach which is based on test pattern generation for each macro, the requirement must be met that the test patterns are made available at the inputs to a macro. This is easy in the case of PLA 1, PLA 3 and PLA 4, shown in Fig. 2, but difficult in the case of PLA 2. Since PLA 2 is fed by PLA 1 and PLA 3, any test pattern required at in...