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# Fast BCD Multiplication Logic

IP.com Disclosure Number: IPCOM000088699D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 218K

IBM

## Related People

Maholick, AW: AUTHOR

## Abstract

The fast BCD (binary coded decimal) multiplication logic described uses table lookup procedures for each digit of the multiplier and multiplicand to obtain the product of the two digits. An array of BCD adders is then used to obtain the partial sums of each multiplier and the multiplicand. Finally, an array of BCD adders is used to form the product from the partial sums.

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Fast BCD Multiplication Logic

The fast BCD (binary coded decimal) multiplication logic described uses table lookup procedures for each digit of the multiplier and multiplicand to obtain the product of the two digits. An array of BCD adders is then used to obtain the partial sums of each multiplier and the multiplicand. Finally, an array of BCD adders is used to form the product from the partial sums.

Fig. 1 shows two registers, A and B, each capable of holding eight digits which are stored in a BCD (8421) format. The contents of the two registers when multiplied together are capable of forming a 16-digit number, which will be stored in register C.

To obtain the product of each digit of the multiplier and the multiplicand a ROS (read-only storage) module is used. The ROS module has 8 bits of input and 8 bits of output. The inputs are 4 bits for the multiplier digit and 4 bits for the multiplicand digit. The output is 8 bits, which represent the product of two digits in accordance with the Table. Thus, for the example shown in which Registers A and B both contain all 9's, the inputs to all ROS modules are 99 and the output is
81.

The results of each partial multiplication must be added, as shown in Fig. 2A, to obtain the product. An array of BCD adders is used to obtain the product. The first partial product is obtained by adding the high digit of the output of each ROS module with the low digit of the ROS module to its left; i.e., R0S (11) 8 + ROS
(21) 1 = 9. Each BCD adder takes 8 bits (2 BCD digits)...