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Double Track Error Correction with a Cyclic Redundancy Check Code for Magnetic Tapes

IP.com Disclosure Number: IPCOM000089303D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 72K

IBM

Chen, CL: AUTHOR

Abstract

This is a double-track error connection scheme using a (72,56) cyclic redundancy check (CRC) code.

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Double Track Error Correction with a Cyclic Redundancy Check Code for Magnetic Tapes

This is a double-track error connection scheme using a (72,56) cyclic redundancy check (CRC) code.

A code word is arranged in a 9-by-8 rectangular array on a 9-track tape, as shown in Fig. 1. The code word consists of eight 9-bit characters. The last character is the CRC check character. The eighth bit of a character is an odd or even parity check of the character and is called VRC check bit.

Let B(i)(x) be a binary polynomial of degree 8 whose j-th coefficient is the j-th bit on the i-th character of a code word. The (72,56) code is defined by its VRC and the equation, Sigma/7/(i = 0) B(i)(x) x/7 - i/ = 0 mod g(x), (1) where g(x) = x/9/ + x/6/ + x/5/ + x/4/ + x/3/ + 1. Single-track error correction for the code is known. Presented here is a correction scheme for double-track erasure errors in which double-track error positions are given.

Let E(i)(x) and E(j)(x), i > j represent the error patterns at track positions i and j, respectively. The degrees of both E(i)(x) and E(j)(x) are less than 8. Define S(1) (x) = E(i) (x) + E(j) (x), and S(2) (x) = E(i) (x) x/i/ + E(j) (x) x/j/ mod g(x). Syndrome S(1)(x) is known from VRC, and syndrome S(2)(x) is computed from the linear feedback shift register (CRCR) shown in Fig. 2, according to (1). With i and j known, E(i)(x) and E(j)(x) are to be obtained. Let A(x) = (S(1)(x) + S(2)(x)X/-j/) mod g(x) over 1 + x The following procedure is used to determine E(i)(x) and E(j)...