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Point Josephson Junction Supply Resistor

IP.com Disclosure Number: IPCOM000089398D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

The use of small point Josephson junctions 1 biased in the so-called RNN region as supply resistors (R(s)) for logic is shown in Fig. 1. The RNN region of a small point junction 1 is shown in the I-V characteristic of such a device in Fig. 2. The logic interferometer 2 of Fig. 1 has an I(m)(0) given by I(m)(0) = 4I(0) (1) for a I(0):2I(0):I(0) configuration for three-junction interferometer 2. Consider n-resistor point junctions 1 in series each having an I(m)(0) of Alpha I(0). Thus, to a first approximation: See original.

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Point Josephson Junction Supply Resistor

The use of small point Josephson junctions 1 biased in the so-called RNN region as supply resistors (R(s)) for logic is shown in Fig. 1. The RNN region of a small point junction 1 is shown in the I-V characteristic of such a device in Fig.
2. The logic interferometer 2 of Fig. 1 has an I(m)(0) given by I(m)(0) = 4I(0) (1) for a I(0):2I(0):I(0) configuration for three-junction interferometer 2. Consider n- resistor point junctions 1 in series each having an I(m)(0) of Alpha I(0). Thus, to a first approximation:

(Image Omitted)

The supply voltage in turn can be generated from a stack of Josephson regulator gates 3 of m junctions operating at this gap voltage yielding a power voltage mV(g). Thus, the logic supply current I(g) is given by: I(g) = m over n 4 over 3 Alpha I(0). (3)

Logic typically requires I(g)/I(m)(0) of the order of 0.60 to 0.70 for optimum margins and speed. Writing this ratio as Beta I(g) over I(m)(0) = m over n Alpha over 3. (4) Clearly, it is also required that mV(g) > nV(g) (5)

Equations (4) and (5) completely define the design. For example, with Beta = 2 over 3 and m = 4, n over Alpha = 2 with n < 4, which conveniently yields n = 2 for Alpha = 1. In this example, the supply resistor is formed by two point junctions 1 in series, each having the same area as the smaller logic interferometer junctions.

The advantages anticipated with this approach are:
1) Current level to logic tracks with systematic j(1) v...