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FET Frequency Doubler

IP.com Disclosure Number: IPCOM000089678D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 19K

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

This frequency doubler circuit can easily be implemented in integrated circuit technology to provide an output signal equal to the absolute value of the input signal around a reference level.

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FET Frequency Doubler

This frequency doubler circuit can easily be implemented in integrated circuit technology to provide an output signal equal to the absolute value of the input signal around a reference level.

Two serially connected MOSFET (metal oxide semiconductor field-effect transistor) devices T1 and T2, having betas B1 and B2 and threshold voltages Vt1 and Vt2, respectively, are coupled across a source of power, +V, and ground. The gate electrodes of both devices are commonly connected to input signal VG, and a capacitor C is series connected to the output terminal to provide output signal Vx. In order to provide voltage-doubler operation, the following parameters must be met: +V >/= VG-Vt1, B1/B2 = 1/4, and Vt2 > Vt1.

In addition, the nominal input signal VG should equal Vt2, and the peak-to- peak amplitude of VG should not exceed Vt2-Vt1. The output voltage Vx will be Vt2-Vt1 to (Vt2-Vt1)/2 at double the frequency of VG.

In operation, when VG is greater than Vt2, Vx will be less than Vt2-Vt1 because both devices will be on in the pinchoff mode of operation, and the output Vx will be inversely proportional to VG. When the input is less than Vt2, the output is also less then Vt2-Vt1 since both devices will be turned off and the output will be directly proportional to VG, as it is coupled to Vx by capacitor C.

Differences in threshold voltages Vt1 and Vt2 can easily be achieved in conventional FET processing by selective ion implantation of the device ch...