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# Encoders and Decoders for Two Compaction Codes

IP.com Disclosure Number: IPCOM000090114D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 59K

IBM

Tang, DT: AUTHOR

## Abstract

An encoder is provided for converting a binary code to a code in which there are d 0's between 1's.

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Encoders and Decoders for Two Compaction Codes

An encoder is provided for converting a binary code to a code in which there are d 0's between 1's.

The encoder of Table 1 and drawing 1 operates for d=1. A two-digit pair is converted to three digits. 11, 12 is the input information word and C1, C2, C3 is the code word. There are three modes of operation depending upon the sequence arrangement of 1's and 0's in the succeeding information pair J1, J2. Where C3 is a 1, then J1 is inspected to determine the next mode. The previous code word is described as b1, b2, b3. The value X indicates that either 0 or 1 is satisfactory. Information digits in drawings 1 and 2 are shifted in groups of two and code digits are shifted in groups of three. This method permits use of smaller intervals per digit because the spacing of 0's between 1's reduces the intersymbol interference problem.

In drawing 1, assume 11, 12 are 1, 1 and J1 is 1, and b3 is 0. And 9 is on from 11, 12. Inverter Iv 1 produces a 1 from the value of 0 in b3, so And 3 is on producing a 1 in register C3. And 5 is off so C2 is 0, since Or 4 receives a 0 from b3 and a 0 from Iv 10. And 2 is on to produce a 1 in C1 because Iv 1 is on and And 6 is on. And 6 is on because 11 is 1 and Or 7 is receiving a 1 from J1.

In drawing 2, if the value to the code register is 101, then Or 11 is on from C3 and so I2 is 1. Also, Or 14 is on since C3 and C1 are both 1 to turn on Or 12. Thus I1 is 1.

In connection with table II and dr...