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# Adder Circuit using Negative Carry Out for Generating the Sum

IP.com Disclosure Number: IPCOM000090776D
Original Publication Date: 1969-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 25K

IBM

## Related People

Schmookler, MS: AUTHOR

## Abstract

Usually, the binary sum for two digits is generated by taking the Exclusive-Or of the half-sum of the digits and the carry into that bit position. As the negative carry-in may not be available or may be inconvenient to develop and the negative carry-out is readily available, this adder utilizes the negative carry-out to generate the sum according to the Boolean S = H times Cin + H times Cout where H is the half-sum of the digits A and B. This equation can be rewritten as a product of S = (H = Cin) (H + Cout).

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Adder Circuit using Negative Carry Out for Generating the Sum

Usually, the binary sum for two digits is generated by taking the Exclusive-Or of the half-sum of the digits and the carry into that bit position. As the negative carry-in may not be available or may be inconvenient to develop and the negative carry-out is readily available, this adder utilizes the negative carry-out to generate the sum according to the Boolean S = H times Cin + H times Cout where H is the half-sum of the digits A and B. This equation can be rewritten as a product of S = (H = Cin) (H + Cout).

In similar manner, the negative of the sum function can be written as S = (H Cin) + (H times Cout) or S = (H + Cin) (H + Cout).

As an example, in implementing the second equation in an adder group of three bits (A1,B1). (A2,B2), and (A3,B3), where (A3,B3) represents the high- order column of bits, the generate or propagate function GP/2/(1) is available for bit positions one and two according to the expression GP/2/(1) = (A2.B2) + (A2 + B2) times (A1 + B1).

The half-sum H3 is provided in positive and negative form from the third bit position. The carry-in from the preceding group of bit positions CGin and the carry-out to the next group of bit positions CGout are readily available from the usual look-ahead circuitry. Using these available input signals, the circuit employs three Or's feeding an And to obtain the sum from the third bit position according to the Boolean expression S3 = (H3 + GP/2/(1...