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# Divider With Special Case Detection

IP.com Disclosure Number: IPCOM000091035D
Original Publication Date: 1969-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 40K

IBM

## Related People

Sussenguth, EH: AUTHOR

## Abstract

Division by small numbers such as 2, 3, 4, 6, 8 is a common occurrence in computer programs. There is logical circuitry which accomplishes a divide-by-three operation in one computer cycle. This system takes advantage of this divide-by-three circuitry to realize its potential time savings when the divisor is of the form 2/n/ or 3.2/n/, that is, 2, 4, 8, 16, etc., or 3, 6, 12, 24, etc.

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Divider With Special Case Detection

Division by small numbers such as 2, 3, 4, 6, 8 is a common occurrence in computer programs. There is logical circuitry which accomplishes a divide-by-three operation in one computer cycle. This system takes advantage of this divide-by-three circuitry to realize its potential time savings when the divisor is of the form 2/n/ or 3.2/n/, that is, 2, 4, 8, 16, etc., or 3, 6, 12, 24, etc.

In drawing I, the use of a 16-bit 2's complement number representation is assumed. Unit 1 is a standard fixed-point division unit which receives as inputs numerator N and denominator D and supplies output C the quotient N/D. The assumed time for the standard division unit is ten cycles. Inputs N and D are received on cycle one, and output C is available at the end of cycle ten.

Unit 2 is a test circuit which receives input D at the start of cycle one and supplies an output by the end of such cycle. The first output f is 1 if D is of the form 2/n/ and is 0 otherwise. The second output g is 1 if D is of the form 3-2/n/ and is 0 otherwise. The third output is a signal supplying the value n when P is of the desired form, i.e., when either f or g are 1. When D is not of the desired form, the third output has no significance and is ignored. Drawing III shows the Boolean equations which provide the required output signals and thus constitute a description of Unit 2.

In drawing 1, unit 3 is a divide-by-three circuit. It receives input N on cycle one and provides its output N/3 by the end of such cycle. Unit 4 is a right- arithmetic shift circuit which receives as its inputs the quantity to be shifted and the shift amount n. Such receipt is at the start of cycle two a...