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# Solid State DC Voltage Multiplexing Switch

IP.com Disclosure Number: IPCOM000091916D
Original Publication Date: 1968-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 28K

IBM

## Related People

Furois, PC: AUTHOR

## Abstract

This circuit applies a DC voltage from a single source E IN to many inputs E1, E2, etc. When a negative voltage is applied at terminal E IN, a current flows through resistor R10. Operational amplifier 12 provides an output so long as both inputs are not at the same potential, i.e., 0 volts. In order to bring the negative input of amplifier 12 to 0 volts, a current, opposite in direction to that established in R10, must be supplied from one feedback resistor RF1 or RF2. The particular resistor through which this current flow is established is selected by removing the forward bias of its corresponding gate transistor TG1 or TG2. When RF1 = RF2 = R10, the voltage developed across any one of terminals E1, E2, etc., is equal to the input voltage E IN and opposite in polarity.

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Solid State DC Voltage Multiplexing Switch

This circuit applies a DC voltage from a single source E IN to many inputs E1, E2, etc. When a negative voltage is applied at terminal E IN, a current flows through resistor R10. Operational amplifier 12 provides an output so long as both inputs are not at the same potential, i.e., 0 volts. In order to bring the negative input of amplifier 12 to 0 volts, a current, opposite in direction to that established in R10, must be supplied from one feedback resistor RF1 or RF2. The particular resistor through which this current flow is established is selected by removing the forward bias of its corresponding gate transistor TG1 or TG2. When RF1 = RF2 = R10, the voltage developed across any one of terminals E1, E2, etc., is equal to the input voltage E IN and opposite in polarity. The feedback current is continually adjusted by operational amplifier 12 and transistors T1 and T2. An advantage of this circuit is its temperature stability which is dependent only on RF1, RF2, and R10 and not on any active elements. Any number of outputs can be added, the accuracy and stability being affected by the current leakage of T1 or T2. The only terminal having an output is the one having its corresponding gate transistor TG reverse biased at 0 or a negative potential.

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