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Standard Multiplex Channel Interface

IP.com Disclosure Number: IPCOM000092439D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 34K

Publishing Venue


Related People

Capowski, RS: AUTHOR [+2]


This circuit provides data flow between central processing unit CPU 10 and input/output devices 12.

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Standard Multiplex Channel Interface

This circuit provides data flow between central processing unit CPU 10 and input/output devices 12.

The interface employs two 1-byte registers 14 and 16 which are accessed by both the inbound data bus 20 and the outbound data bus 22. Bus 22 places an address, data or command into address register 14 or buffer register 16. The address or data are transferred to the bus out driver 23 by And's 24 and 28 depending upon which of the gating lines 30 and 31 is energized. Bytes are transferred to the input/output devices 12 by the bus out line. Address, data or status bytes from I/O's 12 are received on the bus in line for transfer to registers 14 and 16. The contents of the registers are transferred to CPU 10 via data buses 32 and 34 depending upon which of the And's 36 and 38 is energized.

In one typical operation an address received from CPU 10 is stored in register 14. From this register 14 the address is transferred by energizing line 30 through And 24, Or 40 to the bus out line. An I/O 12 responding to this address places such address on the bus in line. Address match circuit 42 compares the bus in line with the address register line. An equal comparison signifies an address match, i.e., the correct I/O 12 is selected.


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