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# Arithmetic Logic Unit

IP.com Disclosure Number: IPCOM000093076D
Original Publication Date: 1967-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 68K

IBM

## Related People

Boden, RC: AUTHOR

## Abstract

This circuit predicts parity for And and Or operations in a self-checked type of adder. The adder can handle any number of bits. A four-bit adder is shown. A duplicate carry chain comprises four And-Or circuits 8, 15, 23, and 31. These circuits are connected to an Exclusive-Or XOR tree comprising three XOR's 18, 24, and 36. The output of this XOR tree provides the modulo-2 count of the carries which have occurred in the operation. Three control lines determine the operation performed by the circuit.

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Arithmetic Logic Unit

This circuit predicts parity for And and Or operations in a self-checked type of adder. The adder can handle any number of bits. A four-bit adder is shown. A duplicate carry chain comprises four And-Or circuits 8, 15, 23, and 31. These circuits are connected to an Exclusive-Or XOR tree comprising three XOR's 18, 24, and 36. The output of this XOR tree provides the modulo-2 count of the carries which have occurred in the operation. Three control lines determine the operation performed by the circuit.

XOR line 148 is raised for the Exclusive-Or operation. And-Or line 151 is raised to And. Add line 155 is raised to add. And-Or and XOR lines 148 and 151 are raised for the Or operation. Or 29 produces a transmit function causing a carry to be emitted by the stage. Such occurs whenever a carry enters the position and either or both of the operand bits stand at 1. And 131 produces a generate function. This circuit causes a carry to be emitted by the stage whenever both operands stand at 1. The generate function operates independently of the transmit function, both of these being Ored together in Or 31 to form the carry circuit for each stage of the adder. A third input is added to the And which is connected to the transmit function generator in each stage, the duplicate carry chain only.

This is shown by And's 108, 115, 123, and 231, all being connected to Invertor 34. In this manner, a carry normally produced by the action of the transmit function...