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Translated Associative Memory Addressing Disclosure Number: IPCOM000093482D
Original Publication Date: 1967-Oct-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 55K

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This memory circuit is usable in catalog or associative memory systems.

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Translated Associative Memory Addressing

This memory circuit is usable in catalog or associative memory systems.

An earlier version of this memory appears in U. S. Patent 3,093,814. Tag memory 10 includes three vertical columns of flip-flops comprising tag registers A, B, and C. Another column of three flip-flops serves as input register 12. Each flip-flop in memory 10 has a complementary input labeled C which, when pulsed, flips the circuit to its opposite stable state in the conventional manner.

Assume that the tag 101 is to be entered into the memory. This tag is placed into the flip-flops of register 12. Then a complement pulse is applied by complement pulse generator 34. This causes the tag 101 to be stored in each of the registers A, 13, and C by complementing the respective flip-flops. The second step is to actuate reset pulse generator 36 to apply a pulse to one of the three output lines 36A, 36B or 36C according to whether the tag in register 12 is to be entered into register A, B or C of memory 10. For example, if the tag is to be entered into register C, then generator 36 applies a pulse to line 36C which resets all flip-flops in register C. The third step is to actuate generator 34 to again apply a pulse to all flip-flops of registers A, B, and C. Thus register C is again complemented to the bit configuration 101 and registers A and B are complemented back to their original states. Thus the tag 101 remains in register C but not in any of the other registers. If registers A and B contain something other than all zeros, they return to their original nonzero states since it is a complementing action and not a...