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Synchronous Internal Clock

IP.com Disclosure Number: IPCOM000093572D
Original Publication Date: 1967-Nov-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 49K

Publishing Venue


Related People

Oeters, HR: AUTHOR [+2]


This apparatus in a data receiver synchronizes a counter with data bits being received.

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Synchronous Internal Clock

This apparatus in a data receiver synchronizes a counter with data bits being received.

Counter 10 receives thirty-two timing pulses T1 per data bit as a standard timing reference. Timing pulses T1, T2, T3, T4, T1, T2, T3, etc., are available periodically. The final stage 10E of counter 10 is off when the pulses counted are 15 or less and on when the count is 16 through 31. Data is sampled with the rise of the on side of stage 10E. It is necessary to continuously examine data transitions relative to this sample time and adjust the sample time to maintain it at the center of the bit. The conventions for early or late data transitions are shown near the logic. By eliminating a timing pulse T1 or adding an additional timing pulse to the counter input, the counter can be synchronized with data bits to provide for sampling the received data at the center of the bit.

Data bits are sampled at 14. At time T1, latch 16 is set through And 18 if there is a data bit or reset through And 20 if the data bit is no longer present. The output of latch 16 conditions And's 22 and 24. At time T4, the status of latch 16 is transferred to latch 26. At time T1, latch 26 contains the data sample from a previous time cycle. If the data stored in latches 16 and 26 is the same, presence or absence, latch 30 remains off to condition And's 18 and 20. This logic is employed so that there is only one clock correction per bit time. Latch 30 is reset at the count of 16...