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# Decoding Circuits for Burst Errors and Independent Errors

IP.com Disclosure Number: IPCOM000094500D
Original Publication Date: 1965-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 40K

IBM

Tang, DT: AUTHOR

## Abstract

In a decoding circuit it is possible to use a total of only n stages of shift registers, k stages in an H register and r stages in a G register. It is unnecessary to keep the H register free of error, and hence only n bits are required for processing. As noted in drawing A, the circuit generates the received message after a delay of only n bits. With the error syndrome recognizer containing the Or gate and the And gate of drawing A, an error can be corrected just before it appears at the output.

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Decoding Circuits for Burst Errors and Independent Errors

In a decoding circuit it is possible to use a total of only n stages of shift registers, k stages in an H register and r stages in a G register. It is unnecessary to keep the H register free of error, and hence only n bits are required for processing. As noted in drawing A, the circuit generates the received message after a delay of only n bits. With the error syndrome recognizer containing the Or gate and the And gate of drawing A, an error can be corrected just before it appears at the output.

Drawing A shows a decoding circuit for the binary (7, 3) burst-2 correcting code with the generator polynomial g(x) = x/4/ + x/2/ + x + 1, and h(x) = (x/7/ t 1)/ g(x) = x/3/ + x+1. The circuit has the following features:

1. The circuit contains a total of n shift register states.

2. The G register is connected according to g(x). If D = x/-1/ is considered as the delay operator, then the correction of the G register is described by the transfer function t/ s = g/*/ (D) + 1, where g/*/(D) is the reciprocal polynomial of g(D). Similarly, the correction of the H register is described by the transfer function t'/ s' = h*(D) + 1.

3. During the first n-bit cycle, the error syndrome is generated in the G register. The syndrome of a correctable error is recognized during the second n- bit cycle and is corrected by it.

4. If no correction takes place, the exact received sequence reappears after a delay of n bits. This is tru...