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# Encoding and Decoding Circuits for Dual Codes

IP.com Disclosure Number: IPCOM000094501D
Original Publication Date: 1965-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 70K

IBM

## Related People

Tang, DT: AUTHOR [+2]

## Abstract

If a first code is generated by the polynomial g(x) and g(x) h(x) = x/n/ - 1, and g'(x) = h(x) = x/n/ - 1/ g(x), where n is the code block length, then a second related code, the code generated by g'(x), is said to be the dual of the first code. The degree of g'(x) is generally different from that of g(x) and hence the two codes are usually of different redundancies. This property is of interest when a data transmission system is required which affords several different degrees of error protection. The use of dual codes in such a situation is particularly desirable because it is possible to use much of the same circuitry for both codes. This is accomplished through the use of a new algorithm for generating the remainder of a polynomial division.

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Encoding and Decoding Circuits for Dual Codes

If a first code is generated by the polynomial g(x) and g(x) h(x) = x/n/ - 1, and g'(x) = h(x) = x/n/ - 1/ g(x), where n is the code block length, then a second related code, the code generated by g'(x), is said to be the dual of the first code. The degree of g'(x) is generally different from that of g(x) and hence the two codes are usually of different redundancies. This property is of interest when a data transmission system is required which affords several different degrees of error protection. The use of dual codes in such a situation is particularly desirable because it is possible to use much of the same circuitry for both codes. This is accomplished through the use of a new algorithm for generating the remainder of a polynomial division.

The above encoder and decoder show implementation for operating in two modes and the overall system when g(x) = x/3/ + x + 1 and g'(x) = x/4/ + x/2/ + x + 1, and illustrate the method of handling g'(x). It is noted that in addition to modulo-2 adders, only a tapped delay line is used in encoding and that simple table lookup decoding is used.

The basic decoder delay circuit is the same as in the encoding circuit. Check bits based on the received information bits are generated and compared with the received check bits. The difference can be identified as the error syndrome. The syndromes are mapped into error patterns by a logic circuit. The error pattern is then subtracted from...