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Logic Circuit Disclosure Number: IPCOM000094968D
Original Publication Date: 1965-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 29K

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Related People

Atwood, LW: AUTHOR


In this Nand logic circuit, transistor saturation is prevented.

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Logic Circuit

In this Nand logic circuit, transistor saturation is prevented.

Logical inputs A, B and C are applied to the emitters of multiple emitter transistor T10. If any input A, B or C is down, T10 conducts such as to draw current from the base electrodes of transistors T12 and T14, thus positively rendering them nonconductive. When T12 is nonconductive, its relatively high collector potential renders transistor T16 conductive. Its low emitter potential causes transistor T18 to be nonconductive. At this point of operation, T14 has no effect upon the circuit since it is also nonconductive.

When inputs A, B and C are simultaneously up, T10 is nonconductive. Current flows out of its collector into the bases of T12 and T14 positively causing them to be conductive.

The conduction of T12 and T14 causes a fall in potential across resistor R1, rendering T16 nonconductive. The rise in the potential across resistor R2 renders T18 conductive. The potential on output conductor 20 is thus caused to shift in a negative direction. T14, at this time, is in a saturated conducting state and provides a voltage drop between the collector and base of T18. This prevents T18 from saturating irrespective of output load variations. In addition, the saturation collector potential of T14 being substantially equal to the collector potential of T12, i.e., base potential of T16, positively cuts off T16 and prevents its conduction.

By maintaining T18 out of saturation, the circuit speed...