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# Binary Trigger or Ring Element

IP.com Disclosure Number: IPCOM000095209D
Original Publication Date: 1965-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 30K

IBM

## Related People

Goldschmidt, RE: AUTHOR

## Abstract

This circuit is a settable element which can be used as part of a ring circuit or shift register for binary data. With an appropriate feedback from an output side to its data input, the circuit can also be used as a settable binary flip-flop.

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Binary Trigger or Ring Element

This circuit is a settable element which can be used as part of a ring circuit or shift register for binary data. With an appropriate feedback from an output side to its data input, the circuit can also be used as a settable binary flip-flop.

As shown, the circuit comprises eight Or-Invert's OI. Each is a two-input Or circuit driving an Inverter stage. Thus, when any input is at the more positive signal level of a pair of permissible signal levels, the output is at the more negative signal level. Connection of the outputs of a number of OI' s provides the Or of the more positive outputs. The OI's 1 and 5, OI's 2 and 6, OI's 3 and 7 and OI's 4 and 8 are connected together so that either OI can hold the common output line at a positive signal level.

Clock line 9 having regularly occurring square pulses on it is connected as an input to OI's 1...4. Set 0 line 10 is an input to OI 5. Set 1 line 11 is an input to OI
6. The remaining inputs of the OI's are outputs of other blocks and are as follows. Output 12 of OI's 1 and 5 is an input of OI's 6 and 7. Output 13 of OI's 2 and 6 is an input of OI's 5 and 8. Output 14 of OI's 3 and 7 is an output carrying a signal which is the complement of that stored in the trigger and is also an input of OI's 4, 8, and 2. Output 15 of OI's 4 and 8 is the true output of the trigger and is an input of OI's 1, 3, and 7.

With this configuration, the circuit has four stable states. The circuit switches from one to the other as the clock signal on line 9 changes. Assume an initial state with line 9 down and data line 15 down, i.e., a trigger state of 0. Then OI's 1, 5, and 3 have positive outputs on lines 12 and 14. Now, when the clock signal on line 9 rises, the outputs of OI's 1 and 3 go negative to drop output line 14 negative. This brings up output line 15 of OI 8 to a positive level and indicate...