Browse Prior Art Database

Peripheral Core Memories Disclosure Number: IPCOM000096548D
Original Publication Date: 1963-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 76K

Publishing Venue


Related People

Hanson, NI: AUTHOR [+2]


Core memories are used as peripheral input/output devices external to a computer.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Peripheral Core Memories

Core memories are used as peripheral input/output devices external to a computer.

A single parity-checked data register DR connects the computer and the core memories. Memory locations are numbered in sequence. For example, data in the last location 15 in memory A is continued in the first location 16 of memory B. The computer can request either reading into or writing from specified memory locations such as Read 11 or from sequential locations such as Read +1 following a specified location, namely 11. Read requests are anticipated, successive data being available whether or not actually used. No confusion results from intermixing of read requests and write requests. Further, the current location being requested is determined by the computer without information loss.

Three memories A, B and C can be selected, one at a time, for obtaining access to any one of forty-seven locations. Data is read from an access location by supplying address information from a memory address counter MAC to three memory address registers MAR and to memory select circuits. The desired data appears in a memory buffer register MBR corresponding to the selected memory. For example, if MAC specifies address 1 1, the contents of all three MAR's are set to 11. The memory select circuits select memory A, the MAR-A causing the contents of location 11 to appear in MBR-A. Since all data must pass through the DR, errors can be determined by checking, in a parity generator/checker, the parity of data prior, and subsequent, to entry in the DR.

For every requested read operation from location 12, for example, two successive pieces of data are accessed from two successive mem...