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Method and Apparatus for Injecting Synchronous Hardware Errors Disclosure Number: IPCOM000097590D
Original Publication Date: 2005-Mar-07
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 55K

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Causing hardware errors to verify code error recovery scenarios has been previously done by employing a number of methods such as with a jumper wire probing error points or an array of relay circuits driven by a computer to select which error to cause. All of these prior methods provide an error condition, but lack precision as to when an error is caused and for how long. For example, the "Pocket Robot", in use today can cause one of 32 errors for one millisecond or more but has no feedback information as to the current state of the hardware being injected. Because there is no synchronization between the state of the hardware being injected and the inject itself, the injects are done repeatedly before any error is seen. This "hit-and-miss" process is not cost effective as it takes longer to produce the desired results, if they are achieved at all. The subject invention is a combination of logic that can generate pulses of various widths and patterns. A hardware multiplexer of FET switches coupled with logic that observes the state of the hardware being injected with an error and is primed with an encoded error to send out when the condition is met. A given hardware circuit is selected as the target of the error. It could be one of several on the target hardware, limited only by the number of analog switches employed. Once a given hardware state is detected by the observational logic, the targeted hardware circuit is driven either high or low, depending on which state produces the desired error. The error is held in place for a specified duration and then released. After the error is observed and appropriately dealt with, another circuit is targeted and the process is repeated. The advantages of this method over previous methods is that the error is placed in time relative to the current state of the hardware being injected with the error. The result of this improvement is that the injection of errors is more likely to yield the desired code error recovery sequence. This reduces the number of attempts that the testing organization needs to perform to produce the desired results.

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Method and Apparatus for Injecting Synchronous Hardware Errors

Hardware fault injection as a testing methodology has existed within the computer storage technology industry for many years, and as system have become more fault-tolerant it has become a major portion of the testing process, particularly when the unit under test has as one of it's design claims the ability to detect, isolate, and report any hardware faults without impacting the overall function of the storage device nor altering the customer's data. Compounding the complexity of testing such behavior is the fact that the functions within the storage devices have become more and more complex and interdependent, with error recovery procedures having to handle increasingly interwoven processes and timing-dependent scenarios. It has become necessary to be able to test the error handling behavior of the unit under test while performing certain unique and independent functions. It is also desirable to be able to verify that the desired machine state has been stimulated by the fault injection. In order to do so, it is required to be able to synchronize the fault simulation stimulus with the code/hardware such that reliable, predictable and verifiable testing results can be claimed. The subject invention uses a hardware feedback mechanism to not only synchronize the fault injection, but to verify that the desired machine state has been achieved through said hardware feedback mechanism.

Hardware running

Target circuit A to be injected with an error

PC running error inject sequences.



 State Observation and Error generation Hardware compares current hardware state with predetermined condition, sends predefined error code when condition met.

Error Injection Multiplexer


State of hardware sent to observation logic

When predetermined condition is met an encoded error is sent to the error injection multipexer.

Target circuit B to be injected with an error

Target circuit C to be injecte...