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# Parity Check Circuit

IP.com Disclosure Number: IPCOM000098569D
Original Publication Date: 1959-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 50K

IBM

## Related People

Higby, LC: AUTHOR

## Abstract

The circuit is utilized to form an ODD parity check on binary words where the bits of a word occur as shown in the Table. That is, bits 1-3 occur in parallel during gate BG1, bits 4-6 during BG2, bits 7-9 during BG3 and bits 10-12 during BG4. Each group of three parallel bits is supplied from amplifiers 10, 11 and 12. For illustration, bits 1, 2 and 3 of the word are shown respectively as outputs of amplifiers 10, 11 and 12. The NOT condition (indicated by a bar over the bit) of each bit is also produced. Switches 13-16 and 17-20 are connected to receive the amplifier outputs and,in addition, parity bits P and P bar for the previous bit gate. The feedback on BG1 reflects initial parity (no bits) of the incoming word and must always represent an even number of bits (P bar).

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Parity Check Circuit

The circuit is utilized to form an ODD parity check on binary words where the bits of a word occur as shown in the Table. That is, bits 1-3 occur in parallel during gate BG1, bits 4-6 during BG2, bits 7-9 during BG3 and bits 10-12 during BG4. Each group of three parallel bits is supplied from amplifiers 10, 11 and 12. For illustration, bits 1, 2 and 3 of the word are shown respectively as outputs of amplifiers 10, 11 and 12. The NOT condition (indicated by a bar over the bit) of each bit is also produced. Switches 13-16 and 17-20 are connected to receive the amplifier outputs and,in addition, parity bits P and P bar for the previous bit gate. The feedback on BG1 reflects initial parity (no bits) of the incoming word and must always represent an even number of bits (P bar).

The outputs of the switches are mixed by OR circuits 21-23 and supplied to an emitter-follower 24. The output of the emitter-follower. is relatively positive, if an odd number of bits are supplied by the three bits in parallel and the previous parity bit. The output is relatively negative, if an even number of bits are supplied by the three bit; in parallel and the previous parity bit. The output is sampled in a switch 25 by a clock pulse, which occurs near the end of each of the bit gates BG1-BG4. An output from switch 25 turns the trigger 26 ON. If, however, the output from the emitter-follower is negative, it is inverted in inverter 27 and sampled by the clock pulse in switch 28 to turn the trigger OFF.

The output from trigger 26, which is r...