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Method for detecting errors on PCI Bus Disclosure Number: IPCOM000099013D
Original Publication Date: 2005-Mar-09
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 86K

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Disclosed is a method to attach a passive logic device to the necessary control signals on the PCI bus and decode the relevant cycles. The solution described below is relevant on any PCI bus that contains multiple bus masters. In the case of bad data parity being signaled on the bus the logic device will see this signal and generate an error condition to the appropriate place to get the desired result, which is all operations stopped and user notified. The advantage of this solution is that it only looks for the error signals when they are relevant, as defined by the PCI specification. Current implementations wire directly to an edge sensitive input such that a glitch on the line will look like an error. The PCI specification is very specific as to when these types of errors are to be signaled. They are always synchronous and only happen at a specific clock during the cycle. The current implementation turns a signal that is supposed to be synchronous into an asynchronous signal, thus leaving open the chance for false errors. This basic design architecture can be used to solve a wide variety of PCI spec violations because it incorporates the main control signals that are needed to de code most PCI cycle.

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Method for detecting errors on PCI Bus

    The logic function of this device is implemented using a programmable logic chip. The chip is placed and routed onto the target bus just as if it is another PCI device. The inputs to this device are the following PCI signal: IRDY, TRDY, DEVSEL, STOP, FRAME, PCI_RESET, PERR and SERR. These are the main control signals for the PCI bus. In this case we are trying to find a data parity error which is signaled by PERR. Using the above control signals the logic device can decode a read/write cycle. By decoding this cycle the device can then start watching for the end of the data cycle. At the end of the data cycle the device can then look for a valid PERR to be signaled. PERR is only signaled two clocks after the last data transfer. If a valid PERR signal is seen the device generates an output signal with can routed to the system to generate an SMI/NMI, depending system needs. Figure 1 below shows the timing of a typical data cycle ending in PERR generation. Figure 2 shows a typical PCI bus layout.

Figure 1 Timing Diagram


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