System With Buffers for 1-To-N Switching of Data Packets

System With Buffers for 1-To-N Switching of Data Packets

       A system is disclosed for switching variable-size packets
from a single input channel to a number, changing, of time division
multiplexed CTDM output  The system, which incorporates a RAM-based
buffer and a mechanism with pointers to that storage, is to store the
arriving packets in a set of logical FIFO and to dispatch the stored
packets over the intended output channel.  The system can operate at
high speed, a flexible and simple implementation, and uses standard

      The figure shows the structure of the system.  The to the
system are: Data/pkt- an 8-bit bus carrying of incoming packets,
Cha#/pckt- and address bus the output channel number which is the
destination the incoming packet, Clock- an external clock for both
input channel and the TDM output channels.  The output of an 8-bit
data bus, Data/slot, carrying the bytes outgoing packets over the TDM
output channels.

      The Channel Data Buffers unit stores packets from the of their
arrival to the system and until their over one of the output
channels.  Its storage is partitioned into a number of contiguous
equal size every buffer corresponding to an output channel. every
buffer, arriving bytes are stored contiguously the last buffer
location being followed, in wrap-around by the first location in the
same buffer.  Every has two pointers associated with it: a read
pointer to the oldest byte, and a write pointer pointing to byte
following the newest byte in the buffer.  These are stored in several
storage units for pointers, explained below.

      The Slot counter takes the external clock as input and a TDM
slot number.  The Slot/Channel Map is a unit which maps TDM slot
numbers into channel  This allocation of TDM slots to output
channels, may change from time to time, is managed by an controller
(not shown).

      The arrival of packets to the system and the departure packets
from the system occur simultaneously and of each other.  During any
clock cycle, it may necessary to use pointers associated with the
arrival of to one buffer, while it may be necessary to use associated
with the departure of packets from a buffer.  In order to accommodate
multiple accesses the pointer storage, there are three storage units
for W-table for write pointers, R1-table and RO-table read pointers
(these last two always have identical

      Updating of pointers is necessary after every read or operation
to buffers.  The updating is performed by W-Ptr Update Logic and
R-Ptr Update Logic.  In order to the highest rate of operation for
the system, a technique is used in which the processing of is
overlapped with accesses...