Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Described is a fault tolerant method usable for busses that are discriminated through addressing. In technologies, multiple drivers driving a same net to directions are destructive to the circuits. This prevents this potential destruction.
a fault tolerant method usable for busses
that are discriminated through addressing. In technologies, multiple
drivers driving a same net to directions are destructive to the
circuits. This prevents this potential destruction.
lines selecting one of eight chips is common and
is used as an example. In this scheme, a chip addressed (the address
matches ID signals) a poll with a common line and continues the By
adding simple parity, a fault on these is possible to detect.
to this set up make it fault-tolerant. all
receiving chips check parity all the time. This all chips to detect
errors on the address bus at the time. Second, each chip must only
acknowledge a poll a common bus) when they recognize their address
Since a stuck
bit only effects half the addresses, half chips
still use the common bus. The chips that do not their address with
good parity stay off the common - do not acknowledge
The system still
operates using only the
receiving that tolerate the fault. This allows limited for customer
operation. Also, since these check the bus all the time, they detect
errors for chip's addresses. Because they are able to use the they
report an error when polled.
checking the parity of the address before may not be
feasible with timing constrain...