Selectable Hardware at Reset Using LSSD Scan Inputs in a Component

Selectable Hardware at Reset Using LSSD Scan Inputs in a Component

       A hardware configuration permits a reset state of Level
Sensitive Scan Design (LSSD) latch to be configured an input pin or
pins of a Very Large-Scale Integration component.  The input pin(s)
are held to a value that determined by external hardware.  Therefore,
the reset is determined by the hardware configuration.

      Fig. 1 shows the hardware configuration with an treatment of a
scan line 6 on a Polarity-Hold Register Latch (PHSRL) 4.  An input 2
to chip 4 is into scan line 6 just before the 1 input.  The effect
input 1 is then removed by AND-OR gating of the output that output is
sent on to the next 1 input in the line 3.

      There are several effects to gating the scan lines in way.
First, at reset state it is possible to force the of the gate to be
at a state determined by an input  Second, when reset goes away, the
output remains at reset state until the latch is set by an ordinary
means. during test mode, it is possible to toggle the latch an
ordinary LSSD test pattern.  The function of this is explained below
for these three operations.

      At reset state, the A-Clock and B-Clock are flushed solidly
active), and the C-Clock is toggled.  A scan input 1 is held at a
zero value.  This forces the value the I-input, which is the value of
input pin 2, to be through the latch.  The output of AND-OR gate 3,
is '1' regardless of what input pin 2 is held at.  The 30 a...