Densest DRAM Cell
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
An open bitline DRAM cell with an area of only 4 lithographic squares, and a processing scheme to fabricate this dense cell is disclosed. Although the open bitline cell results in inherently poorer signal to noise ratios, the factor of two advantage in density over the folded bitline cell is an attraction. For the disclosed cell, most of the critical levels are self-aligned.
Densest DRAM Cell
bitline DRAM cell with an area of only 4
lithographic squares, and a processing scheme to fabricate this dense
cell is disclosed. Although the open bitline cell results in
inherently poorer signal to noise ratios, the factor of two advantage
in density over the folded bitline cell is an attraction. For the
disclosed cell, most of the critical levels are self-aligned.
Description A schematic vertical cross section and top
view of the proposed new cell are shown in the figure. The storage
capacitor is placed inside the trench. The inside polysilicon and
the substrate together form the cell plate. The outer polysilicon
forms the other capacitor electrode and is connected to the
source/drain of the access device through the lateral diffusion. The
access transistor is formed on one side of the trench sidewall.
Since the lateral diffusion is confined to one side of the trench
sidewall, the cell-to-cell punchthrough leakage is avoided, and cells
can be packed very closely. The source/drain at the top of the
trench is formed by outdiffusing from cobalt silicide. The SiO2
insulation on the top of the trench isolates the storage node from
the wordline. The Si3N4 layer insulates the wordline from the
bitline contact. The bitline contacts are self- aligned to the
wordline and the isolation trench. Isolation Trench (IT) is used for
device isolation. The trench depth is about 4.5 mm. The proposed
cell uses only one level of metal. However, a second level of metal
may be used to strap the wordline at regular intervals.
Outline The cell fabrication procedures are given
below. The process sequence can be modified for either an N-array or
a P-array with CMOS peripherals. As described it assumes an N-array.
The approximate process parameters given are for the processing with
a minimum lithography dimension of 0.35 mm.
(1) A low resistivity P-substrate is used. IT lines are formed. The
n+ diffusion area is formed by forming cobalt silicide followed by
I/I and outdiffusion. (For the peripheral devices, gate oxide is
formed after IT, followed by peripheral gate poly.) About 750 nm of
SiO2 and 50 nm of SiO3N4 is blanketly deposited. Using wordline
mask, grooves are etched in the stack formed by SiO2 and Si3N4, by