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Interrupt Service Latency Minimization Disclosure Number: IPCOM000099796D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 5 page(s) / 155K

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McDermott, LF: AUTHOR


This article describes a method for improving interrupt service in a personal computer system by minimizing the interrupt service latency time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Interrupt Service Latency Minimization

       This article describes a method for improving interrupt
service in a personal computer system by minimizing the interrupt
service latency time.

      The method disclosed herein maximizes the computer system's
ability to prioritize interrupt service response time and minimize
device poling.  It enables systems to prioritize the importance of
servicing interrupts when the system is configured.  It also provides
a mechanism which requires one bus cycle to identify the devices on
an interrupt level requesting service.  One bus cycle per interrupt
level is required to identify all devices requesting interrupt
service.  Operating system support and interface are required.

      Systems which support prioritizing interrupt response time must
implement an interrupt controller which arbitrates for control of the
bus.  All masters must contain an architected control register to be
informed that interrupt service has been provided for them.
Interrupt device logic must be implemented to decode the interrupt
identification address and drive an acknowledgement signal on the
data bus.

      This method is a protocol which identifies bus slaves
requesting interrupt (IRQ) service without using serial polling
techniques to identify the device.  The protocol allows up to 16
interrupting devices per interrupt level. All interrupts on a level
are queried in parallel during one bus cycle.  Interrupt service
control is centralized to facilitate multi-tasking operating

      To facilitate the ability of a system to prioritize the
importance of servicing interrupts, the system's interrupt controller
may be configured to arbitrate for control of the bus.  An
arbitrating interrupt controller must contain programmable option
select (POS) registers.  When the system interrupt controller gains
control of the bus through arbitration, it utilizes the system master
as its third party master.  To facilitate the ability to guarantee an
adequate number of bus cycles of interrupt service, the controller's
fairness option may be disabled.

      To maintain compatibility with current systems, interrupt
levels 3, 4 and 7 are reserved for devices which do not support this
method.  Devices interrupting on these levels must be identified
through the use of serial polling techniques.

      Bus masters which support applications using interrupting bus
devices are responsible for monitoring the interrupt lines and
identifying service being provided for its applications.

      The following is a list of characteristics of systems and
devices which support this method:
      1.   The overall system operating software (SOS) and the system
master (arbiter "FF") perform all interrupt service activity.  The
SOS is the software which manages the global system environment (OS,
DOS, etc.).
      2.   The interrupt controller is a system function. There is
only one interr...