Browse Prior Art Database

Full LSSD Synchronizable Clock Divider

IP.com Disclosure Number: IPCOM000100428D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Authors:
Desrosiers, B Renard, J [+details]

Abstract

The disclosed clock divider has the following features: 1. Divide by two the frequency of an input clock. 2. Provide a way to synchronize internal clocks on an external strobe referenced C_CLK that has to be active three periods after reset goes inactive. 3. Insure the non-overlap between the master and slave clocks respectively referenced as "B" and "C' in maximizing the usable time. 4. Be fully LSSD.