Large Elastic Buffer
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
This article describes an elastic buffer fabricated from a random-access memory (RAM), clocks and control circuit. The elastic buffer can be used to compensate for jitter caused by stations on a local area network (LAN).
Large Elastic Buffer
describes an elastic buffer fabricated from
a random-access memory (RAM), clocks and control circuit. The elastic
buffer can be used to compensate for jitter caused by stations on a
local area network (LAN).
The logic is divided into two parts. The first part refers to
the source logic and is synchronous with the incoming data stream,
which is applied to a voltage-controlled oscillator (VCO) to generate
the input VCO clock. The second part illustrates the sink logic and
is synchronous with the crystal which generates the XTL clock used to
time the output data stream.
elastic buffer is implemented in a Token Ring LAN,
since only one station on the ring uses a crystal to clock the data
stream, then in the long term the input data to the monitor station
is synchronous with the output data produced under control of its XTL
clock. However, in the short term, some frequency deviation can
occur due to variations introduced by each station as it derives its
clock from the incoming data stream. These variations can accumulate
to the point where, in the worst case, as much as 50 bits of data
can be 'late' or 'early'.
variations must be accommodated by the master station to
preserve the integrity of the data stream. This is done by storing
the incoming data stream in a continuous or cyclic buffer and reading
it out as required. If the two sets of counters, named Source (SRC)
and Sink (SNK), are initialized to be diametrically opposed, then the
maximum variation can be accommodated. For example, if the source
counters are initialized to '00' and the sink counters to '80', then
they are separated in either direction by '7F'.
The buffer is
said to fail, i.e., overrun or underrun, if the
counters encroach on some minimum difference. A comparator is
applied to the two counters, and if some significant number of bits
are equal, then an error signal is generated and the counters are
re-initialized to their opposing values. In such a case the data
stream has been garbled and a recovery mechanism must be provided to
reinstate the network.
performance and circuit density considerations dictate that
a RAM operation will require two clock cycles. Since both source and
sink will require service every sixteen bit times, then there will
nominally be four cycles required out of every sixteen. Due to the
fact that the clocks are asynchronous, the source request may be
delayed in successive operations until it occurs just before a sink
request. If it occurs one cycle before a sink request, it must be
delayed until after the sink operation is complete, since two
consecutive cycles are required.
the source requests occur faster than the sink
requests, then when they are generated during a sink request, they
will be delayed until they occur at least two cycles before. When
this happens, a sink operation will...