Dual-Function Memory Control Signal
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Publishing Venue
IBM
Related People
Abstract
This article describes a dual-function memory control signal that supports 256K and one megabit dynamic RAMs (DRAMs) without requiring an extra signal pin.
Dual-Function Memory Control Signal
This article
describes a dual-function memory control
signal that supports 256K and one megabit dynamic RAMs (DRAMs)
without requiring an extra signal pin.
The
multiplexing scheme disclosed herein provides support for a
680 X 480 256 color video mode. The
amount of memory required to
support this particular video mode is 307,200 bytes. Two
configurations provide the required amount of memory. The first
configuration consists of two banks of 256K bytes, providing a total
of 512K bytes. This configuration uses
256K bit DRAM memory chips
configured as 64K by 4 bits. This DRAM
technology provides the speed
and storage capacity required. The
second configuration is a
one-megabit DRAM configuration made up of a one-megabyte bank of
memory which uses DRAM chips configured as 256K by 4 bits.
The control
interfaces for the two types of DRAMs are the same
except that the 512K configuration requires an extra column address
signal (CAS) to perform bank selection, while the one-megabyte
configuration requires an extra address bit (A8). Normally, two I/O
signal pins would be required to provide the extra CAS and address
signals. The scheme of this disclosure
combines these two signals on
a single I/O pin. This is done because
I/O pins are limited, and
only one of the two signals would be used in any given
implementation. The present scheme frees
the second I/O pin to be
used for another function.
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