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# Multiple-Valued Logic Identity Element Encoder/Decoder

IP.com Disclosure Number: IPCOM000100874D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 107K

IBM

## Related People

Barcelo, P: AUTHOR [+2]

## Abstract

This article describes a multiple-valued logic (MVL) function whereby a processor input signal is decoded as an identity element on one of the output lines. Also, a MVL device is disclosed that can encode identity element inputs into one output.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple-Valued Logic Identity Element Encoder/Decoder

function whereby a processor input signal is decoded as an identity
element on one of the output lines.  Also, a MVL device is disclosed
that can encode identity element inputs into one output.

MVL systems are logic systems in which the radix > 2. There is
a need to establish building blocks to form the basis of MVL
designing.  This includes defining several functional blocks with no
binary equivalents.

MVL algebra, also known as Postian algebra, defines several
logic operators that can be implemented as gates for digital systems
with a radix 2.  Postian algebra defines the following operators:
A AND B = minimum value of A,B
A OR B = maximum value of A,B
A INVERT = N - 1 - A ; N = radix of system
A CYCLE B = (A + B) mod N

These operators form the basis for MVL designing. Functional
expressions can be defined through the use of these operators in much
the same way as binary functions can be represented by Boolean
algebra.

Another operator used here is the EQUAL function gate. This
function is defined as:
If A = B, then C = N-1; else, C = 0.

Disclosed herein are two MVL devices; an MVL identity element
decoder (MVL-IED) and an MVL identity element signal encoder (MVL-
IESE).

The first type is the N type MVL-IED shown in Fig. 1. This MVL-
IED has one input and N outputs.  It has an output for each of the
logic levels at input x.  Each output generates an identity element
for each of the logic levels (0,1,...N-1).  For example, if a level
of 2 is present at input x, then output line Y2 will generate an
identity element while all other outputs will be a level 0.  When
input x is at level 0, then output line Y0 will generate an identity
element.  Therefore, there will always be one output line generating
an identity element.

The second type is the N-1 type MVL-IED shown in Fig. 2.  This
MVL-IED has one input and N-1 outputs.  It has an output for each of
the log...