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# Multiple-Valued Logic Arithmetic Components

IP.com Disclosure Number: IPCOM000101023D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 8 page(s) / 237K

IBM

## Related People

Barcelo, P: AUTHOR [+3]

## Abstract

This article describes circuit arrangements for various functions performed in multiple-valued logic (MVL).

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This is the abbreviated version, containing approximately 32% of the total text.

Multiple-Valued Logic Arithmetic Components

functions performed in multiple-valued logic (MVL).

MVL algebra, also known as Postian algebra, defines several
logic operators that can be implemented as gates for digital systems
with a radix 2.  Postian algebra defines the following operators:
A AND B = minimum value of A,B
A OR B = maximum value of A,B
A INVERT = N - 1 - A ; N = radix of system
A CYCLE B = (A + B) mod N

These operators form the basis for MVL designing. Functional
expressions can be defined through the use of these operators in much
the same way as binary functions can be represented by Boolean
algebra.

Fig. 1 is a block diagram of a MVL EQUAL function circuit
disclosed herein.  This circuit has 2 inputs a and x and 1 output Y;
the output = N-1 when both inputs have the same value, otherwise, the
output is 0.

An implementation of an MVL EQUAL function circuit is shown in
Fig. 2.  The input signals 'a' and 'x' are subtracted from each other
by the differential amplifier stage.  The resulting difference is
labeled as + or - delta v.  This voltage difference is sampled by the
two comparators.  Comparator 1 compares the voltage difference with
the negative threshold voltage -Vth.  Likewise, comparator 2 compares
the voltage difference with the positive threshold voltage +Vth.  If
both comparators detect that the voltage difference falls within the
acceptance zone defined by +Vth at the upper boundary, and -Vth at
the lower boundary, then a logical comparison has been made.  If the
voltage difference falls within this zone, the outputs of both
comparators produce a voltage level representing a logic level of (N
- 1); this in turn passes the N - 1 through the output of an
MVL AND gate.

A full adder circuit implemented in multi-valued logic is shown
in block diagram in Fig. 3.  The circuit introduces a MVL block for
representing the carry function produced by the addition of two
multi-valued inputs.  The net result is a circuit that reduces
processing time and provides a reduction of logic stage circuits, as
compared with binary full-adder circuits.  Inputs A and B are the
primary inputs. Input CI and the output CO are the carry input and