Browse Prior Art Database

Fixed-Parity Pseudorandom Number Generator

IP.com Disclosure Number: IPCOM000101440D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Authors:
McAnney, WH [+details]

Abstract

Disclosed is a circuit for generating fixed-parity pseudorandom numbers by modifying a linear feedback shift register (LFSR). An example is shown in Fig. 1, in which the block marked SRL is an LSSD shift register latch and XOR is a modulo-2 adder. Fig. 2 lists the two cycles of the fixed-parity generator of Fig. 1.