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Method for a cylindrical chip capacitor Disclosure Number: IPCOM000101630D
Publication Date: 2005-Mar-16
Document File: 9 page(s) / 237K

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Disclosed is a method for a cylindrical chip capacitor. Benefits include improved functionality and improved performance.

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Method for a cylindrical chip capacitor

Disclosed is a method for a cylindrical chip capacitor. Benefits include improved functionality and improved performance.


              Chip capacitor placement on a substrate (die-side capacitor or land-side capacitor) is not required because chip capacitors can be embedded in the substrate.

      Conventional central processing unit (CPU) packages require 10-20 chip capacitors on the substrate for decoupling. A higher count is expected to be required for future CPUs due to their higher performance, including high frequency, high power, and low supply voltage. The substrate surface area available for chip capacitor placement is limited, making smaller chip capacitors advantageous.

      The implementation of smaller chip capacitors requires a new mounting tool at assembly sites.

      Decreased electrical performance can occur due to floating inductance. Chip capacitors with lower impedance are required close to the die.

      An array capacitor is under development. This thin-film capacitor (TFC) is an integrated type in a small sheet layer that includes more capacitors with capacitance varying characteristics. However, the cost is extremely high.

General description

      The disclosed method is a cylindrical ceramic capacitor shaped by rolling the ceramic dielectric materials and inner electrode.

      The key elements of the method include:

•             Capacitor embedded in a substrate core layer by fitting in a through-hole during the substrate manufacturing process

•             Two terminals on the capacitor top and bottom


              The disclosed method provides advantages, including:

•             Improved functionality due to providing a cylindrical chip capacitor

•             Improved functionality due to reducing the chip capacitor placement area on the substrate surface

•             Improved performance due to improving equivalent series resistance/equivalent series inductance (ESR/ESL) by shortening the termination

Detailed description

      The disclosed method is a cylindrical capacitor that fits into a plated through-hole (PTH) to improve substrate space usage and electrical performance (see Figure 1). The cylindrical capacitor has a shorter inner electrode length than the conventional two-terminal multilayer chip capacitor (MLCC).

      The disclosed method is comprised of two core elements, the manufacturing process and the usage of the cylindrical chip capacitor into the substrate core material.

Manufacturing process

      The conventional BaTiO3/bare metal MLCC material set is used for the disclosed method but the configuration of parts and the stacking/lamination process are unique. The manufacturing process includes the following steps:

1.   Parts preparation – Three kinds of parts are used for the cylindrical chip capacitor. Inner layers A and B are made by tape casting the green sheet (BaTiO3). The inner electro...