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High-Performance CMOS Register Disclosure Number: IPCOM000101718D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 130K

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Groves, R: AUTHOR [+1]


Disclosed is a CMOS register designed for high performance. It consists of a latch bit, a priority port select decode and a clock gating network.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-Performance CMOS Register

       Disclosed is a CMOS register designed for high
performance. It consists of a latch bit, a priority port select
decode and a clock gating network.

      The latch bit is shown in Fig. 1 and consists of a pass device
multiplexer (mux) driving an L1 latch which then drives an L2 latch.
Pass device multiplexing into a light load has consistently been
shown not only to be extremely area efficient but also to insert the
least delay into the data path.  Integrating the pass device mux into
the latch captures a light load and in addition allows a polarity
hold function which does not depend upon stopping the clocks. These
advantages are well known and have proven in the past to be well
worth the increased control complexity.

      Single port latches consisting of a double inverter pair and
pass device data entry and feedback paths are also well known and
have practically become industry standards since they offer both high
performance and high packing density.

      The unique difference between prior implementations and the
latch disclosed consists of the addition of a complementary clocked
pass device (T7 and T8) in series with the pass device multiplexer.
Prior implementations do not include these devices but instead butt
the multiplexer to the gate of the latch inverter.  The key advantage
of the latch bit implementation disclosed is that the addition of
devices T7 and T8 makes register timing independent of decode
circuitry and therefore more predictable and controllable.  This, in
turn, improves register performance since it reduces the clock skew
otherwise introduced by additional clock gating levels in the decode

      Pass device multiplexing requires that no more than one pass
device be on at any one time to prevent DC current paths in signal
lines.  In the past, this requirement has been met with a full port
select decode in which, for example, two controls are applied to a 1
of 4 decode.  This scheme has two basic disadvantages:
      1.  The encoding of selects into addresses essentially confuses
the one-to-one correspondence between the desired action and its
invocation and, in addition, encoding selects also degrades register
performance due to the additional circuitry introduced into the
select path.
      2.  The priority select decode shown in Fig. 2 eliminates these
disadvantages.  Although priority decodes have been used in the past
for other purposes, they have not been used in prior art as register
port selects.  A performance gain is realized with a priority decode
since it does not require port select encoding in the logic that