Hardware-Implemented Single-Step for Microprogrammed Processor
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Publishing Venue
IBM
Related People
Hoover, RD: AUTHOR [+4]
Abstract
In a Tightly Coupled Multiprocessor environment, a problem may be encountered on one of the processors in the system. Because of this there exists the need to analyze one processor while the rest are inactive. In order to ensure instruction execution will occur on one processor while the others are stopped, the other processors must be at an instruction boundary. This is necessary to ensure no 'locks' are active between processors which would halt operation. This article describes the implementation of a scheme to allow one processor to be analyzed while the others are inactive.
Hardware-Implemented Single-Step for Microprogrammed Processor
In a Tightly
Coupled Multiprocessor environment, a
problem may be encountered on one of the processors in the system.
Because of this there exists the need to analyze one processor while
the rest are inactive. In order to
ensure instruction execution will
occur on one processor while the others are stopped, the other
processors must be at an instruction boundary.
This is necessary to
ensure no 'locks' are active between processors which would halt
operation. This article describes the
implementation of a scheme to
allow one processor to be analyzed while the others are inactive.
Features are:
-
allows single-processor analysis in a tightly
coupled multiprocessor environment,
-
instruction boundary stop function implemented
entirely in hardware,
-
less complex than a microcode solution to
instruction single stepping,
-
better performance than the microcode solution,
-
not dependent on microcode debug before use
This
disclosure is implemented in hardware manual-ops. First,
all processors are stopped at the desired time. Clocks and microcode
are not controllable to a single processor.
When they are stopped
(started), they are stopped (started) on all processors at the same
time.
The
instruction stepping routine (which is a Hardware Manual
Op) starts by the Service Processor scanning in the correct values
into all processors in the system. The
processor to be analyzed (Px)
will have the 'Stop' latch scanned to the 'on' position. (Refer to
the figure.) This will halt operation by
causing an infinite hold
off in that processor even when clocks and microcode...