Browse Prior Art Database

IP.com Disclosure Number: IPCOM000102223D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 39K

IBM

## Related People

Kwangil, K: AUTHOR

## Abstract

Described is a method which speeds up the floating-point (FP) multiply operation in an iterative multiplier by generating 4 bits per iteration when the multiple terms are simple.

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Described is a method which speeds up the floating-point
(FP) multiply operation in an iterative multiplier by generating 4
bits per iteration when the multiple terms are simple.

This method looks at 4 bits of the multiplier and the
carry-over from the previous iteration and decides the 4-bit or 2-bit
advancing multiple at each iteration.  If the multiple chosen is a
4-bit multiple, it advances 4 bits at that iteration; if it is not,

In order to explain how it works, let us look at the 4-bit
multiplier more closely.  If there is only one 1 in the 4 bits, such
as 1000, 0100, 0010 and 0001, the multiples are accordingly:  8, 4,
2, and 1.  Also, if these numbers are subtracted from the lowest
multiple of the next iteration (b'10000' or d'16'), then 1000, 1100,
1110 and 1111 would exist.  Since they can be rewritten as 16-8,
16-4, 16-2, and 16-1, then -8, -4, -2, and -1 for the current
multiple and carry- over for the next iteration would exist.  The
multiple for 0000 is obviously 0; therefore, 8 combinations out of
the 16 possible combinations can be predicted (refer to Fig. 1).

If one of the other 8 combinations exists, it simply looks at 2
bits and generates the 2-bit multiple; in this case, it advances only
2 bits (refer to Fig. 2).  Since the probability of having a 4-bit
multiple is about 50 percent (assuming the random distribution over
the FP fraction), it i...