Very Fast General-Purpose Bank Select Generation

Very Fast General-Purpose Bank Select Generation

       Disclosed is a means to generate Multiple Bank Selects
with only three levels of logic.  (Although any logic can be designed
in 2 levels, gates with an extremely large number of inputs are
impractical.)  Also, in this method, any Bank may be any allowable
size and ALL the memory can be configured contiguously.  The base
address for a bank must be an even multiple of the bank's size.

      In this method of decode, there is one Configuration Register
per Bank.  The Configuration Registers have two fields:  the base
address field and the bank size code field.  Fig. 1 shows the 3
levels of logic for one bank select.  The first level of logic (2
input AND gates) masks off irrelevant bits.  The second two levels
compare the masked address to the base address.

      Fig. 2 shows size codes for a 32-bit address, where the 8 most
significant address bits are used in the bank decode. There are 8
size code bits that correspond to the 8 address bits used in the bank
decode.

      To configure the memory contiguously, the largest banks of
memory must be at the lowest address (closest to address
'00000000'x).  As the address of the banks increases the size of the
banks must decrease or stay the same.  Fig. 3 shows the correct and
an incorrect way to configure a 16-Meg and a 32-Meg Bank for
contiguous memory.  In the correct example the larger bank (32-Meg)
is at address '00000000'x and the 16-Meg bank...