Laser-Ablated Resist Via Inspection
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Publishing Venue
IBM
Related People
Collini, GJ: AUTHOR [+3]
Abstract
Disclosed is a technique to remove organic material, such as photoresist, over an integrated circuit to get qualitative and quantitative information on developed via patterns in a polymer stack (located in a kerf area) prior to other subsequent operations, i.e., wet etching or RIE.
Laser-Ablated Resist Via Inspection
Disclosed is
a technique to remove organic material, such
as photoresist, over an integrated circuit to get qualitative and
quantitative information on developed via patterns in a polymer stack
(located in a kerf area) prior to other subsequent operations, i.e.,
wet etching or RIE.
The Problems
Solved with This Technique
-
Practical inspection of high-aspect-ratio via-type structures.
(This inspection will become more difficult as the technology
continues to advance into the submicron region.)
-
Necessity to use a destructive method of inspection
(mechanical cross section).
-
Difficulty in determining if the via holes are open by
standard optical microscope or SEM inspection.
See Figs. 1 and 2.
Fig. 1 shows an SEM vertical, and Fig. 2 shows an SEM tilted.
State of the
Art Standard optical microscopy and even the SEM
tilt-stage can only give top image inspection.
Cross sectioning is
the only current pos- sible method to get information, such as
sidewall profile and bottom image details, of via holes with high
aspect ratios.
One
photocleave technique [1,2] requires the use of a stepper,
masking, double exposure prior to developing of the vias; this
produces an undesirable rounded edge image, making it difficult for
critical measurements.
The drilling
of macro via holes in polyimide and the sectioning
of the via using the laser-ablation technology has also been
demonstrated [3].
Description
of the Technique Depending on photoresist materials
an optional strippable water- soluble top coat is applied on the
photoresist-coated wafer, to keep the debris generated during the
ablation process from falling on the device area and into the via.
After the ablation process the optional top coat is removed by water
rinse. See Figs. 3 and 4. Fig. 3 shows a
via without a top coat,
and Fig. 4 shows it with a top coat.
The via chain
located in the kerf area is ablated using an
adjust- able...