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Multi-Clock Rate Device for Hardware Simulation Efficiency Improvement Disclosure Number: IPCOM000102633D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 158K

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Disclosed is a system that increases cycle simulation performance and efficiency.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Multi-Clock Rate Device for Hardware Simulation Efficiency Improvement

       Disclosed is a system that increases cycle simulation
performance and efficiency.

      Context Actual big hardware machine developments use design
methodologies based on Technology-Independent (T.I) logic (described
with assignment, conditional skip and branch statements) and
synthesis to a chosen target technology.

      The logic is partitioned into several functional islands which
are developed in parallel by different designers.

      A large part of the development schedule is dedicated to
simulation. It begins on isolated islands, then goes up with larger
and larger structures to reach functions grouping different cards of
the future machine.

      As there is no more delay notion in a T.I implementation, the
design methodologies use cycle simulators which are more performing;
their principle is that the whole logic is activated only at its own
clock cycle, no state change occurring between. If all clocks are the
same, the logic is activated each simulation cycle which is equal to
the clock rate of the logic; if not, the user must adjust all island
clockings by calculating their highest common factor (HCF) and
converting their own cycle according to it.

      All the islands are not ready to be connected at the same time
unless many of the problems occur on interfaces. Thus, at the
beginning of each project, a simulation plan is established with the
definition of simulation devices named models that represent subsets
of functions of the different interfaces to allow the designers to
simulate their logic before the one it really interfaces is

      With our actual T.I. methodology, these models are described in
the same language as the logic; they are thought of as if they were
logic parts. The only difference is that they will probably not be
converted to chips later although their algorithms and implementation
could be used as it is in hardware parts.

      Problem description Two logics L1 and L2 are connected on both
sides of a serial link S with a specific protocol. Bit time on S is
240 Ns. L1 is running at 30 Ns, L2 at 40 Ns.
      Fig. 1 shows the logic interconnection.

      To simulate L1 and L2 independently of each other, it is
necessary to develop a serial link model MS whose function is to send
and interpret data to/from L1 and L2 according to the protocol, until
L1 and L2 are ready to be connected.
      Fig. 2 shows the necessary connections.

      Due to the complexity of such a model, it is unacceptable in
terms of resources to develop two versions of it and to maintain

      Now, imposing one of the 2 rates would automatically degrade
the simulation performance for the logic running with the other one:
 o If MS is clocked at 30 Ns, one simulation cycle represents
      -    30 Ns (Bit time/8) for L1 simulation, both L1 and MS being
activated each cycle...