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Improved Methods for Inter-Chip Clock And Data Distribution Disclosure Number: IPCOM000102712D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 137K

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A local voltage-controlled oscillator (VCO) is used on each slave chip in a system to generate clock waveforms for clocking logic circuits on that chip.

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This is the abbreviated version, containing approximately 52% of the total text.

Improved Methods for Inter-Chip Clock And Data Distribution

       A local voltage-controlled oscillator (VCO) is used on
each slave chip in a system to generate clock waveforms for clocking
logic circuits on that chip.

      A single clock synchronization net is fed from the system
master chip out to all slave chips in the system. This net carries a
synchronizing waveform which consists of relatively fast but
infrequent transitions, typically occurring once per system clocking

      Clock generator logic on the slave chips generates short window
pulses once per system cycle. These pulses are then compared with the
incoming synchronization waveform in a phase comparator circuit,
which in turn adjusts the frequency of the VCO via a time constant
(T), thus forming a phase locked loop which synchronizes the on-chip
clocking cycle with the incoming waveform.

      This system offers significant advantages where many high-speed
clock pulses need to be generated for each system cycle and fed to
multiple chips. If the clock signals were all generated on the master
chip, it would be necessary to have a clock net transition for each
clock pulse required in the system. These transitions must be fast to
ensure good clock accuracy, and require a charge or discharge of the
entire clock net capacitance each time, this energy being dissipated
in the driver circuit. The capacitance of such a net is not small, as
several chips are involved, and significant driver power may be
consumed just in the distribution of high-speed clocking information.

      Other disadvantages are that the need for large, powerful clock
net drivers causes power transients and adds to EMC problems, also,
noise or reflections on the clock distribution nets contribute
directly to clock jitter.

      The synchronized scheme can in fact use a much slower
transition for the single synchronizing waveform, as any jitter due
to this is very effectively averaged out by the phase comparator time
constant which adjusts the VCO frequency. A smaller net driver
circuit can thus be used, with consequent reduction in noise and
power transients.

      Depending upon how frequently the synchronizing waveform
transition occurs, substantial clock distribution power savings can
result.  For a high-speed system extending over several chips, where
the capacitance of each net joining the chips might be 100 pF, the
energy associated with charging or discharging such a net through 5
volts would be some 1.25 nJ, dissipated in the net driver each time
the net is raised or lowered. For distribution of a clocking scheme
consisting of 1.25 ns pulses, we would need a theoretical power of at
least 1 watt on the clock chip drivers to supply distribution net
transitions at such a rate for a conventional clocking scheme. For
the synchronized scheme, in contrast, using say a transition every 50
ns on a single synch net, only 25 milliwatts clock driver power is