Growable Register Array for High-Density CMOS Applications
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-17
Described is a technique providing a high-density solution for small, single-port arrays and a variety of multi-port array applications. In the large-logic chip environment, storage element macros may require special circuit implementation to incorporate some form of an array self-test. The described technique saves much of the area that would normally be devoted to enhance testability of these designs.