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Dynamically Programmable Logic Disclosure Number: IPCOM000104122D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 142K

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Related People

Rubloff, GW: AUTHOR


Disclosed is an approach to enhance chip functionality by dynamic reprogramming of the interconnections between subsections of the chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

Dynamically Programmable Logic

      Disclosed is an approach to enhance chip functionality by
dynamic reprogramming of the interconnections between subsections of
the chip.

      Advanced logic chips are designed to perform preassigned logic
functions and are optimized for performance by minimized critical
paths for those functions.  To accommodate the full function needed
by a complete computer system, the number of part numbers (different
configurations) of logic chips in the system runs into the hundreds,
even thousands, for high performance computers.  This diversity
places a heavy demand on design tradeoffs for optimization of each
chip and on design and testing of so many individual part numbers.

      To ease this problem, smaller macros (portions of chip
performing certain well-defined and generic functions) are often
designed, then full chip designs constructed as interconnections of
these macros.  While this eases the design problem somewhat, part
number counts stay high, and a fully fabricated chip maintains a
fixed functionality for its full lifetime.  A more flexible chip
design/architecture approach might provide significant benefit to
reduce these penalties.

      This invention supplies a possible solution to much of the
above problem by proposing a chip architecture and functionality mode
which allows subsets of the chip (much like macros, and referred to
here as "chiplets") to be wired together dynamically as desired
during the operation of the chip.  Fig. 1 shows a full chip divided
schematically into a number of chiplets, each of which can perform a
fairly generic logic action.  Programmable interconnections are
provided on the chip which allow input/outputs (I/O's) of one chiplet
to be connected to I/O's of other chiplets dynamically.

      The dynamic interconnections between chiplets are envisioned to
function at speeds slow compared to that of the chiplet circuitry;
for example, as the system would see a new application being started,
it could identify a better chiplet interconnection scheme and then
implement it dynamically to optimize performance of the full chip and
system for the application.  By making chips on which the
interconnections between macros could be dynamically reconfigured, it
should be possible to tune the overall circuitry on the chip to
optimize different applications as needed, and it should also be
possible to reduce the number of hardware part numbers needed for a
given system.  Two hardware approaches to the dynamic interconnection
scheme are envisioned:

1.  Dynamic electrical interconnections

    Relatively simple active transistor devices (e.g., simple n-MOS
    or TFT devices) could be employed to make the desired chiplet
    interconnection arrangements.  Since the devices could be
    fabricated at low levels of process technology, they should not
    degrade yield (although some real estate on the chip would be