Prefetching for a Chain of Control Blocks

Prefetching for a Chain of Control Blocks

      Prefetching  for L1-CACHES that are preformed by an L2 cache
using a mechanism based on information derived from the processor at
the time of the L1-D-CACHE miss.  The amount of information can be
extended to include the instruction image, that caused the miss, and
thereby the register number that contained the base address.  This
information might simplify the mechanism and would be useful in
specific implementations.  Our disclosure focus on three "essential"
aspects of the prefetch command: (REG.LOCATION, REGISTER.VALUE,
MISS.TARGET.  ADDRESS) what we call the command triad.

      A superior prefetching strategy for D-CACHE lines is to use

I sub VALUE x D sub VALUE -> D sub LOC
as opposed to
I sub LOC x D sub LOC -> D sub LOC

A means of providing this information when target-D sub LOC becomes
the source-D sub LOC with the same ADDRESS SHIFT INDEX allows for the
prefetching of a chain of control blocks that derive from the
accesses created by a single instruction within a loop.  A single
prefetch mechanism entry indicates this occurrence, templates the
recursion, and allows for change of GPR source location.

IMPROVEMENTS IN I x D -> D PREFETCHING - The manner of improvement in
the D prefetching is to incorporate the value changes and location
changes in the prefetch mechanism.  We realize that -

I x D -> D is a way of expressing
I sub LOC x source-D sub LOC -> target-D sub LOC
which is intended to be a surrogate for the actual Address Generate
(AGEN) operation

I sub VALUE x source-D sub VALUE -> target-
D sub LOC
as these represent:

o      I sub VALUE - the instruction which makes the access,
o      source-D sub VALUE - the value of the GPR, and
o      target-D sub LOC - the line that will be accessed,
respectively.  Now instructions do not change but data can easily be
modified.  The corrected form of the prefetching is
I sub LOCx source-D sub VALUE -> target-D sub LOC
and the prefetching mechanism is organized around the I-LINE, and for
each I-LINE, has a table of triads:
[source-D sub LOC, source-D sub VALUE, target- D sub LOC].  Such a
triad is supplied by the processor at the point of a D-CACHE MISS
that has not be prefetched and derived from a special register bank
within the processor that retains the source of a subset of GPRs that
have not been modified.  The triad also establishes the ADDRESS SHIFT
INDEX that allows the entry to used used when the source-D sub VALUE
is altered.

      Such a prefetch mechanism can prefetch when the I sub LOC is
either accessed or is anticipated to be accessed, and target-D sub
LOC can be anticipated in the following circumstances:

o      [source-D sub LOC, source-D sub VALUE] are both unnchanged.
o      [source-D sub LOC]  is unchanged and [source-D sub VALUE]  is
    changed.
o      [source-D sub LOC, source-D sub VALUE] are both changed.

The rubric for location change builds on the rubric...