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Clock Distribution Tree for Minimal Clock Skew Disclosure Number: IPCOM000104651D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 49K

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Klein, K: AUTHOR [+2]


The distribution of clock signals on a chip is improved for reduced clock skew.

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This is the abbreviated version, containing approximately 69% of the total text.

Clock Distribution Tree for Minimal Clock Skew

      The distribution of clock signals on a chip is improved for
reduced clock skew.

      For this purpose, a clock signal is distributed such that the
interconnections carrying it to the functional subblocks on the chip
have substantially the same length.  This is accomplished by the
clock distribution tree shown in the figure.

      This clock distribution tree has, for instance, three amplifier
stages, such as drivers V1, V2, V3.  For larger chips required for a
complete system, the number of amplifier stages may be increased.
The first stage V1 is placed substantially in the center of the chip
and connected to the input for a clock signal by a net 1.  There is
only a limited number of permissible positions 2 for placement of the
second stage V2.  The second stage may only be positioned on the
boundary of the square having stage V1 in its center.  As a result,
the length of net 2 is independent of the placement of stage V2,
provided only rectangular interconnections are possible.  This
applies by analogy to stage V3, since stage V2 defines the center of
a further square determining the permissible positions 3 for stage
V3.  Thus, the wire length from any of the permissible positions 3 to
the input is equal, so that there is zero skew.

      In each of the amplifier stages V1, V2, V3, a group of, say, 10
drivers is used which are placed in a very dense cluster.  This
results in similar nets of equ...