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Selective Translation Lookaside Table MRU-Update Disclosure Number: IPCOM000105040D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 93K

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Cheng, K: AUTHOR [+3]


Disclosed are techniques for updating the Translation Lookaside Table (TLB) MRU position selectively during cache access.

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Selective Translation Lookaside Table MRU-Update

      Disclosed are techniques for updating the Translation Lookaside
Table (TLB) MRU position selectively during cache access.

      The design of a high-performance superscalar processor normally
provides multiple decode and address generation units with
out-of-sequence execution techniques to achieve less-than-one CPI
(cycle per instruction).  In such design, it requires multiple cache
accesses to sustain the operand-fetch requirement.  An example of a
double execution pipeline in its ideal case is depicted in Figure 1
in which a five-cycle pipe with a two-cycle cache access is assumed.
When the pipeline is full, it can achieve 0.5 CPI.

           |              ....
                          Figure 1.

      An infinite cache is assumed in the above discussion.  With a
finite cache size, the requested data may not always be presented in
the cache.  When such a case happens (called cache miss), a request
is sent to the higher memory hierarchies to move the line into the
cache.  A Least-Recent-Used (LRU) replacement is commonly used to
determine which cache line to be replaced.  Due to program locality,
the cache miss ratios are usually very low in modern processor

A cache access normally consists of three steps:

1.  Address Translation:  Translate virtual addresses to real
    addresses through a Translation Lookaside Table (TLB).
2.  Cache Directory Lookup:  Determine if the line is in the cache.
3.  Cache Array Access:  Access data when cache hits.

      In a virtual cache environment, the virtual address tags are
used for comparison to determine if the accessed line is in cache.
the Translation step is not required upon cache hit.  However, when a
cache miss occurs, the address translation is needed before the
request can be sent to higher memory hierarchies.  There are two
reasons.  First, two virtual addresses may be mapped into the same
real address, which may cause a 'synonym' hit case.  Second, the
higher memory hierarchies can only realize the real address.  Since
the cache hit ratio are very high (normally in the 97-98% range), the
address translation does not perform in most of the cache accesses.
As a result, the number of address translation unit may not have to
match the number of cache access pipes to save some hardware.  Such
mismatch, however, may create a problem in keeping the TLB MRU
information up-to-date for the TLB replacement.  This is du...